1. Field of the Invention
The present invention relates to a method of forming a contact hole for a metal line in a semiconductor device, particularly enabling an improved integrity of the barrier metal at the contact area.
2. Background of the Invention
In a conventional method of forming a metal line in a semiconductor device, the step coverage and the integrity of a barrier metal are deteriorated by a shadow effect of contact hole in a sputtering process of a barrier metal to be deposited on the contact area as the aspect ratio of the contact hole increases.
FIG. 1 shows a partial sectional view of a semiconductor for explanation of conventional method for forming a metal line in a semiconductor device.
As shown in FIG. 1(A), a gate silicon oxide layer 12, a polysilicon layer 13 for a gate, and a cap gate silicon oxide layer 14 are deposited on a silicon substrate 11 in that order.
As shown in FIG. 1(B), the cap gate silicon oxide 14, the polysilicon layer 13, and the gate silicon oxide layer 12 are etched by photolithograpy, to form a gate 13' and a portion of the silicon substrate 11 is exposed.
Then, a source/drain junction 15 is formed at the exposed portion of the silicon substrate 11 by usually an ion implantation and thermal treatment.
As shown in FIG. 1(c), a silicon oxide layer 16 is deposited on a resulting surface, i.e., on the cap gate silicon oxide layer 14, at the side of the gate 13', and the source/drain junction 15.
Then, a side wall spacer 16 is formed at the side of the gate 13' and the cap gate silicon oxide 14 by etching anisotropically the silicon oxide layer 16.
A bit line and a capacitor (not shown) are formed after the side wall spacer 16 is formed, resulting in a height undulation of more than 1 .mu.m between a circuit region and a cell area.
Accordingly, a depth of focus for photo lithography is secured by depositing BPSG 17 or 03-USG(ozone-undoped silicate glass) of more than 5000 .ANG. and then letting it flow for planarization, thus eliminating the undulation.
As shown in FIG. 1(D), an insulating layer 17 is formed on the circuit region to a thickness of more than 1 .mu.m.
As shown in FIG. 1(E), a contact hole 18 is opened onto the source/drain 15 by photolithography, where the aspect ratio of the contact hole 18 becomes more than 2 if the contact hole has a diameter less than 0.5 .mu.m.
As shown in FIG. 1(F), a barrier metal 19 is deposited in the contact hole 18 and on the insulating layer 17 by a sputtering method. Compounds such as Ti, TiN, TiW, and MoSi2, may be used for the barrier metal.
If the aspect ratio of the contact hole is more than 2, the step coverage of the barrier metal 19 onto the source/drain 15 degrades due to the shadow effect of the contact hole 18, resulting in a low integrity of the barrier metal at a corner portion 19' of the contact hole. Sometimes, the barrier metal is not sputtered at a edge, thus a metal formed in the next step contacts directly to the silicon surface.
As silicon in the source/drain 15 and metal of a metal line (not shown, e.g. Al) contact directly at a fringe of the source/drain 15 on which the barrier metal is not deposited, a spiking effect occurs, resulting in a bad contact characteristic.